The present invention relates to a switching circuit of capacitive load. More particularly, it relates to an improvement in the driving circuit for charge multiplication gate of an electron-multiplying charge-coupled-device imaging device.
As the charge-multiplication-gate driving circuit of the charge-coupled-device (which, hereinafter, will be abbreviated as “CCD”) imaging device as well, the driving logic integrated circuit for the CCD imaging device is available if voltage amplitude of the driving-target CCD imaging device is smaller than 5 V. Also, the general-purpose CMOS logic integrated circuit is available if the voltage amplitude is smaller than 6 V (reference should be made to the SONY-fabricated ICX422AL 11-mm diagonal (2/3 type) EIA block-and-white-designed solid imaging device J01X22A41).
In the electron-multiplying CCD imaging device (which, hereinafter, will be abbreviated as “EM-CCD”), the sensitivity can be enhanced by combining the EM-CCD with electron cooling. In the charge multiplication gate (which, hereinafter, will be abbreviated as “CMG”) for performing the electron multiplication of the EM-CCD, however, the following drawbacks exist: For example, in the TEXAS INSTRUMENTS (which, hereinafter, will be abbreviated as “TI”)-fabricated 330000-pixel CMG, when the capacitive load is about 25 pF, the impedance at 12.5 MHz becomes equal to about 509Ω, which is a significantly heavy load. Also, the CMG voltage amplitude falls in a range of 18 Vp-p to 24 Vp-p, which is large and variable. In addition, at the high electron-multiplying time when the CMG voltage amplitude is large, the sensitivity varies by the amount of 1.4 times as a result of a 0.1-V voltage variation. Also, the sensitivity varies by the amount of 1.8 times as a result of a 11-° C. temperature variation. Accordingly, it is requested to ensure the voltage amplitude of the driving waveform, high stability, and reduction in the heat liberation, i.e., power consumed. For example, in the e2V Technology (which, hereinafter, will be abbreviated as “e2V”)-fabricated CMG, the CMG voltage amplitude falls in a range of 35 Vp-p to 45 Vp-p, which is even larger. Consequently, unlike other electrode drivings for the CCD imaging device, it is difficult to utilize the general-purpose integrated circuit whose withstand voltage is equal to about 18 V. In view of this situation, the following technique is commonly used: A pulse waveform is supplied to the CMG for performing the electron multiplication of the EM-CCD via the drain of a complementary enhancement-type metal-oxide-semiconductor field-effect transistor (: MOSFET) whose power-supply voltage is variable. Then, the CMG is driven using the CMOS logic integrated circuit to which the gate of the MOSFET is capacitively connected. Also, in the read-out CMG, e.g., the TI-fabricated 330000-pixel CMG, when the capacitive load is about 85 pF and about 55 pF, the impedance at 12.5 MHz becomes equal to about 150Ω and about 231Ω, which are significantly heavy loads. Accordingly, the integrated circuits referred to as “pin drivers” are used whose voltage amplitude is equal to about 8 Vp-p and whose withstand voltage is equal to about 18 V (reference should be made to the TI-fabricated TC246RGB-B0 680×500 PIXEL IMPACTRONTM PRIMARY COLOR CCD IMAGE SENSOR SOCS087-DECEMBER 2004-REVISED MARCH 2005, and e2V-fabricated A1A-CCD65_Series_Ceramic Issue 7, June 2004). Since the horizontal resolving power lowers at the high electron-multiplying time when the CMG voltage amplitude is large, the CMG voltage amplitude is reduced down to its minimum by cooling the EM-CCD (reference should be made to the Desert Star Systems-fabricated Night and Low-Light Imaging with Frog Eye™ and Shark Eye™ Digital Cameras, Application Note 2nd Edition 280CT05). It is estimated that the lowering in the horizontal resolving power occurs because, at the high electron-multiplying time when the CMG voltage amplitude is large, rectangular-wave characteristics of the CMG deteriorate and thus the horizontal transfer becomes incomplete. Also, there occurs a state which is referred to as “blooming”. In this blooming state, charge carriers, which leak out to a vertical transfer path due to an excessive light amount, overflow one after another to an accumulation-unit transfer path and a horizontal transfer path.
Also, FIG. 7 is a block diagram for illustrating the configuration of a conventional and commercially-available complementary-MOSFET driving circuit (reference should be made to JP-A-2001-298943). In this complementary-MOSFET driving circuit, the conduction time and the non-conduct ion time are made substantially equal to each other for being used as the nominal 12-V battery-input switching power-supply which is designed for the voltage of 10.5 V to 17 V of small-sized automobiles and broadcasting cameras, and for being used for driving the non-multiplication charge multiplication gate Hφ. FIG. 8 is a schematic diagram for illustrating the input/output voltage operation of the conventional complementary-MOSFET driving circuit.
In FIG. 7 and FIG. 8, when an output voltage Vout4 of an IC 4 for driving the gate of a MOSFET becomes equal to 0 V, a diode D6 is brought into the conduction. Accordingly, the gate voltage of a Pch-MOSFEI Q1 is driven by a resistor 5, thereby being caused to exceed a threshold voltage in a comparatively long time. As a result, the Pch-MOSFET Q1 starts the conduction (i.e., turns on). Meanwhile, when the output voltage Vout4 of the IC 4 for driving the gate of the MOSFET becomes equal to 5 V, a diode D7 is brought into the conduction. Accordingly, the gate voltage of the Pch-MOSFET Q1 is driven by a resistor 6, thereby being caused to rise up to the threshold voltage in a short time. Moreover, the gate voltage remains at the threshold voltage until charge carriers have been extracted. Then, the Pch-MOSFET Q1 terminates the conduction (i.e., turns off) in a comparatively long time.
Similarly, when the output voltage Vout4 of the IC 4 for driving the gate of the MOSFET becomes equal to 0 V, the diode D8 is brought into the conduction. Accordingly, the gate voltage of an Nch-MOSFET Q2 is driven by the resistor 7, thereby being caused to drop down to a threshold voltage in a short time. Moreover, the gate voltage remains at the threshold voltage until charge carriers have been extracted. Then, the Nch-MOSFET Q2 turns off in a comparatively long time. Meanwhile, when the output voltage Vout4 of the IC 4 for driving the gate of the MOSFET becomes equal to 5 V, a diode D9 is brought into the conduction. Accordingly, the gate voltage of the Nch-MOSFET Q2 is driven by the resistor 8, thereby being caused to exceed the threshold voltage in a comparatively long time. As a result, the Nch-MOSFET Q2 turns on.
The inter-gate-source capacity of a MOSFET (which, hereinafter, will be abbreviated as “Cgs”) is proportional to the product of the drain-source withstand voltage (which, hereinafter, will be abbreviated as “withstand voltage”) and the drain current capacity (which, hereinafter, will be abbreviated as “current capacity”), and is substantially proportional to the fineness of machining (i.e., design rule) as well. For example, in the 2006-year-mass-produced 30-V withstand voltage MOSFETs, such as the SANYO-fabricated MCH3335 and MCH3435, the Pch peak current capacity is equal to about 40 pF at 1.6 A, and the Nch peak current capacity is equal to about 30 pF at 2.8 A. Also, the gate charge carriers (which, hereinafter, will be abbreviated as “Qg”) are proportional to the product of the withstand voltage and the current capacity, the drain current, and is substantially proportional to the fineness of machining as well. In the above-described 2006-year-mass-produced 30-V withstand voltage MOSFETs, such as the SANYO-fabricated MCH3335 and MCH3435, Qg is equal to about 2100 pC per the 1-A Pch current, and is equal to about 1400 pC per the 1-A Nch current. As a result, the Pch-MOSFET is delayed in its turn-off.
Also, the practical commercialization has been already accomplished concerning the circuit for performing constant-current driving for basic electrodes of the CCD imaging device using bipolar transistors and with a horizontal synchronization period which is slow, i.e., about 600 times as large as the horizontal transfer (reference should be made to JP-A-2001-45384).
By the way, in recent years, in order to reduce unnecessary radiation, the following ferrite bead has been mass-produced in a variety of types: At a low frequency, its impedance is low. Then, from a certain specific frequency, its impedance becomes higher steeply, and its resistance component becomes larger (reference should be made to TDK-fabricated 006-02/20080408/e9412_mmz2012). The approximately equivalent circuit to the ferrite bead is a circuit which is obtained by connecting an in-parallel connection of an inductor, a capacitor, and a resistor to a resistor in series with each other (reference should be made to TDK-fabricated mmz2012 Equivalent Circuit).
There also exists the Schottky barrier diode where the forward-direction drop voltage VF is reduced down to 0.13 V with the reverse-direction leakage current IR remaining reduced.
In the above-described conventional technologies where the conduction time and the non-conduction time are made substantially equal to each other, in FIG. 7, i.e., the block diagram for illustrating the configuration of the conventional complementary-MOSFET driving circuit, in the resistor-in-series diodes D6 to D9 which are connected in series to the resistors connected to the gates of the MOSFETs, the gate driving amplitude decreases by the amount of 1.2 V, i.e., two times as large as the 0.6-V diode forward-direction drop voltage, and thus the gate driving amplitude becomes equal to 3.8 V. This operation is exactly illustrated in FIG. 8, i.e., the schematic diagram for illustrating the input/output voltage waveform of the operation of the conventional complementary-MOSFET driving circuit. In FIG. 8, since impedances of the resistors R3 and R4 are low, the currents R3 and R4 are large. Also, since the value of Qg1 is large, Vcmg becomes unbalanced.
In the switching circuit for driving the charge multiplication gate (: CMG) for performing the electron multiplication of the EM-CCD, the CMG voltage amplitude falls in a range of, e.g., 18 Vp-p to 24 Vp-p, or 35 Vp-p to 45 Vp-p, which is significantly large. Accordingly, the MOSFET is unusable which is used for the battery-input switching power-supply, and for driving the non-multiplication charge multiplication gate Hφ, and whose withstand voltage is low, and whose inter-gate-source (control) voltage at which the conduction resistance substantially saturates is low. The gate voltage at which the ON resistance of the CMG-driving Pch-MOSFET drops is equal to, e.g., 4.5 V, which is significantly high. Consequently, the above-described conventional technologies, where the conduction time and the non-conduction time are made substantially equal to each other, is inapplicable to the CMG driving. On account of this, there occurs a simultaneous conduction time during which the Nch-MOSFET and the Pch-MOSFET are simultaneously brought into the conduction, which gives rise to the consumption of ineffective power. Accordingly, it is expected that the heat liberation amount will increase by the amount equivalent to a significant loss due to the ineffective power, and that the temperature will rise thereby to lower the sensitivity of the EM-CCD. On account of this, instead of reducing the current at which the Nch-MOSFET and the Pch-MOSFET are simultaneously brought into the conduction, an about 33-Ω large-permissible-loss resistor is inserted into between the drains of the Nch-MOSFET and the Pch-MOSFET. Here, the CMG capacity is equal to about 25 pF, and the impedance at 12.5 MHz is equal to about 509Ω. As a result, an attenuation of the CMG voltage amplitude, e.g., 24 Vp-p, is made equal to (24V×509/509+33+2)=22.5 V. Consequently, it turns out that the voltage drop caused by R3, R4, and the CMG in FIG. 7 has been allowed by the amount of as much as 1.5 V. In, e.g., the TI-fabricated TC246, this 1.5-V voltage drop is equivalent to an approximately 1/160th sensitivity lowering. This is because, in the maximum sensitivity operation of TC246, the sensitivity varies by the amount of 1.4 times as a result of a 0.1-V voltage amplitude variation.
Also, like the Desert Star Systems-fabricated product in the Related Art, the horizontal resolving power lowers at the high electron-multiplying time when the CMG voltage amplitude is large. Moreover, the blooming in the horizontal transfer becomes deteriorated.